e
Very Large-Scale Integration Engineer
Responsibilities: Worked for Marvell Semiconductor on the Physical Design of AI accelerators and high-performance processors targeting 3nm and 5nm nodes. Contributed to the Place and Route (PnR) flow for designs exceeding 8M+ standard cells and 50+ macros, optimized for timing, power, and area (PPA) at frequencies above 3.2 GHz. Performed comprehensive Static Timing Analysis (STA) to resolve timing violations and ensure compliance with performance and power requirements. Developed and optimized TCL scripts to automate tasks in PnR and STA, enhancing design efficiency and accuracy. Collaborated with cross-functional teams to achieve timing closure and successful tape-outs, addressing challenges such as IR-drop, crosstalk, DRC, and LVS using industry-standard EDA tools.
Responsibilities: IEEE-HKN is known for its reputation and legacy in Computer Engineering domain from 1904 to till now. Being a Secretary General at Illinois Tech Delta Chapyer my primary roles are to conduct meetings, sending important mails or invitaions, Cross Communication with other board members and guests or panelists etc.
Responsibilities: During my time at ChipEdge, I began as a Physical Design Engineer Trainee, where I received comprehensive training in the field. Upon completing my training, I progressed to an intern role, where I had the opportunity to work on four Industry standard projects: CHIPTOP, Falcon, DTMF, and JBI. Throughout these projects, I diligently employed the Block-Level design methodology and leveraged various Synopsys tools.
Responsibilities: I joined BYJU'S as a BDA trainee and after qualifying i promoetd to Business Developement Associate at Bhubaneswar Office. My day-to-day responsibilities were, Extensive Travelling, Student Counseling, Cold Calling, and Revenue Generation. During my working period I was awarded as a best BDA in terms of revenue Generation.